1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a manner of direct lead bonding.
2. Description of the Background Art
In background-art power semiconductor devices, when a source electrode plate and a drain electrode plate are soldered to a power semiconductor chip, a nickel film is formed between the power semiconductor chip and each of the electrode plates in order to ensure bonding thereof using the solder.
The source electrode plate is provided on the side of a first main surface of the power semiconductor chip. The drain electrode plate is provided on the side of a second main surface of the power semiconductor chip. As the power semiconductor chip, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like may be used.
Such a method as discussed above where the source electrode plate and the drain electrode plate are bonded directly to a predetermined conductive film (nickel film) formed on the power semiconductor chip with no wire therebetween is termed “direct lead bonding”. In recent, the direct lead bonding is adopted more than before to ensure lower resistance of the device.
Further, on the first main surface side of the power semiconductor chip, a predetermined pattern is usually formed. In order to protect the pattern from external forces, a metal layer such as aluminum-silicon or the like is formed between the first main surface of the power semiconductor chip and the nickel film.
On the second main surface side of the power semiconductor chip, formation of the nickel film directly on the second main surface causes a problem that the contact resistance between the power semiconductor chip and the nickel film should be increased.
Then, on the second main surface side, a conductive film having lower contact resistance with the power semiconductor chip (hereinafter, referred to as “low contact resistance conductive film”) is formed between the power semiconductor chip and the nickel film.
When a heat treatment is performed on the power semiconductor device, transverse stresses are exerted on the nickel film and the low contact resistance conductive film. The transverse stresses are caused in accordance with thermal expansion coefficients of the nickel film and the low contact resistance conductive film.
When the low contact resistance conductive film is formed only on the second main surfaced side of the power semiconductor chip as discussed above, however, there arises a difference between a transverse stress caused on the first main surface side due to presence of the nickel film and a transverse stress caused on the second main surface side due to presence of the nickel film and the low contact resistance conductive film. Due to the difference of these transverse stresses, the power semiconductor chip is disadvantageously warped so that its first main surface side should become convex.
In order to relieve this warp of the power semiconductor chip, the low contact resistance conductive film additionally provided on the second main surface side has been formed also between the nickel film and the metal layer on the power semiconductor chip on the first main surface side. In other words, the layered structure consisting of the conductive films formed on the second main surface of the power semiconductor chip is the same as that consisting of the conductive films formed on the first main surface side as viewed from the power semiconductor chip.
Further, one end of an aluminum wire is bonded onto the first main surface side of the power semiconductor chip, besides the source electrode plate. The other end of the aluminum wire is connected to a gate electrode.
Prior arts relating to the structure of the above power semiconductor device are shown in, e.g., FIG. 2 of Japanese Patent Application Laid Open Gazette No. 2002-198515 (Patent Document 1) and FIG. 1 of Japanese Patent Application Laid Open Gazette No. 2003-243585 (Patent Document 2).
The prior-art technique on the power semiconductor device causes complication in manufacture process since a process of bonding the source electrode plate with solder and a wire-bonding process using the aluminum wire have to be performed separately.
Further, in the prior-art power semiconductor device, there are some portions on the first main surface of the power semiconductor chip where no conductive film having the above layered structure is formed (the aluminum wire is bonded in a manner of wire bonding). Therefore, the prior-art power semiconductor device can not sufficiently relieve the warp of the power semiconductor chip.